1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same. More particularly, the present invention relates to a metal-insulator-metal (MIM) capacitor and method of fabricating the same.
2. Description of Related Art
Recently, a semiconductor device for implementing a capacitor with high capacity has been developed for analog circuits requiring high-speed operation. Typically, the capacitor is composed of overlapping upper and lower electrodes and a dielectric layer interposed therebetween. When the capacitor is formed in a polysilicon-insulator-polysilicon (PIP) structure, an oxidation reaction occurs at an interface between the polysilicon electrodes and the dielectric layer and further oxidation occurs due to a subsequent annealing process to change electrical characteristics of the capacitor. Further, the capacitor has non-uniform capacitance depending on a size of a voltage applied to the polysilicon electrodes. For example, when capacitor electrodes are doped with n-type impurities and a negative voltage is applied to the upper electrode, holes are induced to the surface of the lower electrode. Resultantly, a depletion layer may be formed on the surface of the lower electrode, the depletion layer having a width that varies depending on the size of the negative voltage applied. Due to the depletion layer, the capacitance of the capacitor is not uniform and varies depending on the size of the applied voltage. As a result, there are disadvantages in that such a capacitor is not suitable for a semiconductor device having an analog circuit due to the nonlinear characteristic of the capacitance.
A metal-insulator-metal (MIM) capacitor having metal electrodes has been proposed in an effort to solve the above-described problem associated with a polysilicon-insulator-polysilicon (PIP) capacitor. A MIM capacitor is mainly used for a high performance semiconductor device because of its small resistivity and absence of parasitic capacitance caused by internal depletion.
The manufacture of a high performance semiconductor device requires a metal interconnection having low electric resistance and high reliability. MIM capacitors using copper as a material of this metal interconnection have recently been proposed. However, because it is difficult to pattern copper using a reactive ion etching (RIE) method, the metal interconnection is typically formed by a damascene process.
One conventional method of fabricating a MIM capacitor includes forming a MIM capacitor by a dual damascene process. More specifically, in this conventional method, a lower copper interconnection layer and a lower electrode layer are formed within an insulating layer by a damascene process, and then a buffer layer and an inter-metal dielectric (IMD) layer are formed. Photolithography and etching processes are performed on the structure to form a trench that forms a capacitor region. A buffer layer and a dielectric layer are formed in the trench. The buffer layer is further formed on the dielectric layer, and then an etching process is performed to expose the lower copper interconnection through the photolithography and etching processes. A buffer layer is formed to protect the lower copper interconnection region. The lower copper interconnection region and the capacitor region are buried with metal and then are planarized to form a metal interconnection and an upper electrode.
In this method, however, there is still a disadvantage related to fabrication costs due to the photolithography process because a photolithography process for exposing the lower copper interconnection region must be performed in addition to a photolithography process for exposing the upper electrode region.
As a result, there is a need for a method of fabricating a MIM capacitor that is capable of reducing fabrication costs by reducing the number of required photolithography processes.